Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing
Kazuhiko Iwasaki · Systems and Computers in Japan · 1990
Abstract This paper analyzes the rough behavior of aliasing probabilities (missing faults) when the signature testing is applied to CMOS combinational circuits. In the analysis of aliasing probabilities, the fault detection probability for one‐digit test patterns—the fault detection probability—becomes important. However, for general circuits it is difficult to evaluate the fault detection probability. In this paper the circuits are restricted to CMOS combinational circuits, and it is intended for the control circuits for microprocessors. For CMOS logic LSI's, the utilization of combinational gates follows a certain specific frequency and the expected value of the fault detection probability can be calculated. First, the gate usage frequencies are examined for three types of CMOS logic LSI's. Next, the fault detection probabilities of single gates are analyzed. Based on the forementioned results, the fault detection probabilities of simplified κ‐stage combinational circuits are analyzed. As a result, the expected value of the fault detection probability for a CMOS combinational circuit is shown to be 0.4 – 0.5. Using this expected value, the approximate behaviors of the aliasing probabilities for the signature testing are presented for MISR's and single‐input LFSR's applied to CMOS combinational circuits. In particular, for single‐input LFSR's it is shown that within the range of practical use, the aliasing probabilities are not monotonic.