Selective instruction compression for memory energy reduction in embedded systems
Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino · 1999
We propose a technique for reducing the energy required by firmware code to ezecute on embedded systema. The method ia based on the idea of compressing the moat commonly ezecuted instructions 80 a ~ to reduce the energy dissipated in memory acceeees. Instruction decompression is performed on the fly by a hardware module located between processor and memory: No changea to the processor architecture ore required. Hence, our technique is well-suited for systema employing IP cone whose internal architecture cannot be modified. We describe a number of decompnaaion achemea and architec-tura that effectively trade off hardware complezity for memory energy and bandwidth nduction, aa proved by experimental data collected by executing aeveml sample programs. 1