A class of multiprocessors for real-time image and multidimensional signal processing
Tony Denayer, Etienne Vanzieleghem, Paul G. A. Jespers · IEEE Journal of Solid-State Circuits · 1988
A 90000-transistor, 50-MIPS (million-instruction-per-second) multiprocessor chip designed for image orthogonal transform is discussed. The architectural principle, derived from a tensorial formalism, is usable for the other linear processings of multidimensional signals (e.g. n-dimensional convolution). A regularity factor of more than 99% was obtained by taking advantage of systolic principles at both chip and bit levels.>