A design of online scheme for evaluation of multinomials
Pouya Dormiani, David Omoto, P. Adharapurapu, M.D. Ercegovac · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2005
We present an online arithmetic scheme for hardware evaluation of multinomials arising in Bayesian networks. The design approach consists of representing the multinomial in a factored form as an arithmetic circuit which is then partitioned into subgraphs and mapped to FPGA hardware as a network of online modules connected serially and operating in overlapped manner. This minimizes the interconnect demand without a drastic increase in computation latency. We developed a partitioning/mapping algorithm, designed basic radix-2 online operators and modules, and determined their cost/performance characteristics. We also evaluated the cost/performance characteristics of implementing a Bayesian network on an FPGA chip.