Design of a SOC for low cost IC testing
Liakot Ali, Roslina Mohd Sidek, Ishak b. Aris, Rahman Wagiran, S. Muqthiar Ali · 2004
This paper presents the design of a SoC for low cost IC testing using verilog HDL. Conventional IC tester, ATE, is based on deterministic algorithm. With the continuous increase of integration densities and complexities in IC technology, ATE reveals serious drawbacks and point towards having a new approach in IC testing for its economic and reliable solution. Recently researchers have shown that dynamic reseeding based mixed-mode (DRM) approach outperforms all other existing test technologies. The SoC is designed implementing the DRM technique. It is capable of testing combinational circuits as well as sequential circuits with scan-path facilities efficiently. It can also be used for testing PCB interconnection faults.