Leveraging Wire Properties at the Microarchitecture Level
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John Phillip Carter · IEEE Micro · 2006
In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip data transfers to the most appropriate wires, thus improving performance and saving energy