An iterative division algorithm for FPGAs
Jianhua Liu, Michael Chang, Chung‐Kuan Cheng · 2006
Division is one of the most complicated and expensive arithmetic operations. Both clock frequency and operation delay are limited by the memory wall, even in LUT-based FPGA devices. To conquer the memory limitation, we propose a hybrid division algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms. The proposed algorithm boosts very-high radix division efficiently. The algorithm is multiplicative, and feasible for the modern FPGA devices with build-in multipliers. The algorithm is implemented in Altera StratixII FPGA devices and compared with the division IP core generated by MegaWizard. The result shows that the PST algorithm has higher clock frequency, lower execution time and also lower power consumption.