Precision Timed Embedded Systems Using TickPAD Memory
Matthew M. Y. Kuo, Partha S. Roop, Sidharta Andalam, Nitish D. Patel · 2013
There has been a great deal of impetus for the design of predictable memory such as scratchpad memory. Moreover, static analysis of cache memory is an area of intense research activity. However, there has been minimal development of caches or scratchpads (SPMs) that can exploit the inherent concurrency in synchronous languages. In this paper, we have developed a new memory subsystem, called the TPM (TickPAD memory), for predictable and efficient execution of synchronous programs. TPMs are a hybrid between conventional caches and SPMs: they support dynamic loading of cache lines (like caches) and static allocation of program points (like SPMs). However, the dynamic loading is predictably managed through statically loaded TPM commands. Extensive benchmarking comparing TPMs to SPMs and direct mapped caches reveal that TPM achieves 8.5% WCRT reduction compared to locked SPMs, 12.3% WCRT reduction compared to thread multiplexed SPM and 13.4% WCRT reduction compared to direct mapped caches, while also keeping the analysis time comparatively small.