ECL fault modelling
Carlo Morandi, Lorenzo Niccolai, F. Fantini, S. Gaviraghi · IEE Proceedings E Computers and Digital Techniques · 1988
A procedure for describing an ECL circuit at the gate level is proposed. All voltages and currents which switch during circuit operation are described by logic variables, and thus the ‘stuck line’ model can be effectively applied to describe circuit failures. Faults resulting from open connections and short circuits between transistor terminals are considered in detail.