SfW method: Delay test generation for simple chain wrapper architecture
Marcel Baláž · 2010
The aim of the presented work is to improve the quality of testing of SoC digital cores surrounded with test wrappers. The paper presents a new effective delay fault test generation method for the transition faults based on the skewed-load test. The generated delay fault test can be applied to a SoC core through a test wrapper architecture with only a simple boundary scan chain. This eliminates the necessity to use an enhanced boundary scan chain for the application of the delay fault test. The effectiveness of the developed method for a transition delay test generation was verified on the set of combinational and sequential circuits. The experiments show a significant reduction of test vector application time.