Functional testing of LSI gate arrays
Glen D. Vaughn · Design Automation Conference · 1974
This is a report on the testing of LSI gate arrays. A large number of combinational and sequential digital networks were tested using the traditional s-a-1, s-a-0 faul t model. These random logic functions were implemented with LSI gate array devices. This report describes the environment within which these devices were tested and the testing results. Also, some problems encountered in testing these devices and solutions to these problems are summarized.