A systolic-array architecture for first-order 4-D IIR frequency-planar digital filters
Randeel Wimalagunarathne, Arjuna Madanayake, Donald G. Dansereau, Len T. Bruton · 2012
A novel parallel semi-systolic semi-scanned array architecture is proposed for the implementation of four-dimensional (4-D) IIR filters. These filters have emerging applications in computed tomography (CT), volumetric ultrasound, and light field processing for computer vision. The proposed architecture can be applied to a broad class of 4-D IIR filters, and we show results for a frequency-planar depth-selective filter. Our implementation is on a Xilinx Virtex-6 xc6vsx315t-3ff1156 FPGA, and is suitable for filtering of a N1× N2= 4 × 4 aperture light field camera input. Results compare favourably with ideal and FPGA-hardware measured outputs, with an N1N2factor increase in throughput compared to a corresponding fully raster-scanned design clocked at the same clock frequency.