On IIR‐based bit‐stream multipliers
Chiu‐Wa Ng, Ngai Wong, Hayden Kwok‐Hay So, Tung-Sang Ng · International Journal of Circuit Theory and Applications · 2010
Abstract We analyze the existing bi‐level IIR‐based bit‐stream multiplier and propose selection criteria for the key design parameter governing droop and phase linearity. Based on the proposed choice of parameter, we then extend the bi‐level design to tri‐ and quad‐level architectures that offer better signal‐to‐noise performance. Hardware complexity and noise performance of these designs are also contrasted with previously proposed FIR‐based bit‐stream multipliers. Useful design guidelines are subsequently drawn. Copyright © 2010 John Wiley & Sons, Ltd.