Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method
Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman · 2014
Reversible logic synthesis has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate faults (MMGF), are likely to be more suitable for modeling defects in quantum k-CNOT gates. This work proposes an algorithm for deriving the test set for the detection of all single missing gate faults in a reversible circuit implemented with k-CNOT gates. Instead of deriving test set directly for the detection of missing gate faults, a Boolean generator is developed by Boolean difference method to derive the test set and to detect all the single missing gate faults of a reversible circuit. Experimental results on some benchmark circuits are also reported.