Circulating Packet Threshold Logic To Implement Msd Logic Modules
David L. Flannery, L. Maugh Vail, Steven C. Gustafson · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1986
Threshold logic element designs in circulating packet form are presented for the implementation of addition and subtraction using modified sign digit (MSD) arithmetic. This arithmetic is attractive for digital optical computing due to its inherent parallelism and pipelining characteristics, which capitalize on natural strengths of optics. To illustrate application of these concepts, a design for CORDIC rotation modules to accomplish the complex Givens rotations required for systolic array QU matrix factorization is presented. This design accomplishes QU factorization using only threshold logic elements and bit-shift operations in a systolic configuration. Although implementable in principle by either electronic or optical means, the design is amenable to optical implementation because it involves high levels of parallelism and interconnections.