MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache
Mark Horowitz, Paul Chow, Don Stark, Richard Simoni, Arturo Salz, Steven A. Przybylski, John LeRoy Hennessy, Glenn Gulak, Anant K. Agarwal, John M. Acken · IEEE Journal of Solid-State Circuits · 1987
MIPS-X is a 32-b RISC microprocessor implemented in a conservative 2-/spl mu/m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includes a 2-kbyte on-chip instruction cache. The authors provide an overview of MIPS-X, focusing on the techniques used to reduce the complexity of the processor and implement the on-chip instruction cache.