The dynamically reconfigurable CAP Array Chip I
Steven G. Morton, Enrique Abreu · IEEE Journal of Solid-State Circuits · 1986
Array Chip I is a bit-slice processor chip using novel fault-tolerant, large-area integration techniques. It provides 20 1-bit bit-slice processors, or cells, which are controlled from a single microinstruction stream. The chip is implemented in 3-/spl mu/m double-metal n-well CMOS, has 115000 transistors, and an unusually large die size of 500/spl times/650 mil. Prototype yields, with at least 16 cells operational exceed 25%. The chip configuration is controlled by software at run time to form bit-parallel or bit-serial words of arbitrary size and to exclude defective elements. Following system initialization, defective elements are invisible at both the programming and the physical chip interconnect levels. Thirty-six of these chips have been used in a prototype cellular-array parallel processor employing the single-instruction stream, multiple-data stream (SIMD) architecture.