Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only)
André Seffrin, Sorin Alexander Huss · 2012
Dynamic partial reconfiguration allows the exchange of hardware configurations on FPGAs at run-time. Within a reconfigurable system that supports several different modules, resource requirements for interconnect between these modules may be considerably high. Enabling communication via a crossbar may require too many resources. State-of-the-art modelling methods for partial dynamic reconfiguration already support the fine-grained description of interaction between the partial modules. We propose both an online and an offline method for automatically generating interconnect according to such communication constraints, aiming at a low resource usage. The online algorithm determines an appropriate port assignment for the partial modules by means of a greedy approach and exploits port overlaps. The offline algorithm employs simulated annealing in order to find a proper port assignment and also incorporates the scheme for exploiting port overlaps. Constraint-generated interconnect requires significantly less resources than a crossbar, even if only a random port assignment is used. Proper port assignment by the online method reduces these requirements by an additional 10%, and using the offline method reduces them by an additional 30% on average. Online port assignment is faster than the offline method by several orders of magnitude. The interconnect generation tool introduced in this work takes textual input of communication constraints and automatically generates a corresponding hardware description in VHDL.