Multiplication over F p m on FPGA: a survey
Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto · 2007
Abstract. This paper aims at comparing multiplication algorithms over Fpm on FPGA. Contrary to previous surveys providing the reader with an estimate of both area and delay in terms of XOR gates, we discuss placeand-route results which point out that the choice of an algorithm depends on the irreducible polynomial and on some architectural parameters. We designed a VHDL code generator to easily study a wide range of algorithms and parameters. 1