Multi-path routing in time-division-multiplexed networks on chip
Radu Stefan, Kees G. W. Goossens · 2009
The exponential increase in transistor count due to technological progress has resulted in an increase in complexity and processing power of on-chip elements. Recently a stage has been reached where it is not practical anymore to increase the core size, and as a consequence the number of cores, processing elements or peripherals is being increased instead. In this study we focus on improving the efficiency of a network between those processing elements using alternative routing strategies. We focus on a multi-path slot allocation method in networks with static resource reservations, in particular networks on chip (NoC) employing time-division multiplexing (TDM). The simplicity of these networks makes it possible to implement this routing scheme without significant hardware overhead. Our proposed method, although displaying large variations between test cases, provides significant overall gains in terms of allocated bandwidth, with an average gain across all tests of 29% against an exhaustive search of single-path routes, and gains of 47% when compared to other single-path routing algorithms.