Automated Design Error Localization in RTL Designs
Maksim Jenihhin, Anton Tšepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, J.-H. Meza Escobar, Heinz‐Dietrich Wuttke · IEEE Design and Test · 2013
This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.