A compact direct digital frequency synthesizer for system-on-chip
Cao Xiaodong, Ni Weining, Ling Yuan, Zhikun Hao, Yin Shi · 2008
A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98% using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter (DAC) has been successfully implemented using standard 0.35 um CMOS process. The core area of the DDFS is 1.6 mm2. It consumes 167 mW at 3.3 V, and its spurious free dynamic range (SFDR) is 61 dB.