A programmable power-efficient decimation filter for software radios
Emad N. Farag, Ran-Hong Yan, M.I. Elmasry · 1997
Several high-level low-power design techniques have been incorporated in the design of a decimation filter for software radio.These include; operation minimization, multiplier elimination and block deactivation.Analysis and simulation results indicate that these techniques can achieve a 4 times reduction in power dissipation.An interleaved multiplier-accumulator array is used in the lowpass filter.The decimation filter designed has a programmable resolution, that varies from 12 to 20 bits.The entire decimation filter has been designedin a 3.3 Volt O.~/.UZZ CMOS technology.-. -..