Implementation of fault simulation and testing of combinational circuits
Sushmita Mitra, Banani Saha · International Journal of Electronics · 1989
A software implementation of a logic simulator capable of testing combinational circuits is presented. Exhaustive testing methodologies like syndrome and index vector testing are applied to make the testing procedure simpler. However, a-tests and b-tests have to be generated and applied in the case of index vector untestable circuits. The method is capable of handling both single and multiple faults. Sample runs have also been included.