Design and verification of mixed-signal I/O IPs: an 12C bus controller
Olivier Romain, T. Cuenin, Patrick F. Garda · 2004
The external communications between a system on a chip and its environment require mixed-signal intellectual properties such as bus or wireless interfaces. Their behaviour respects the bus protocol, in time, in packet length, in access mode. We describe in this paper firstly the design of an intellectual property (IP) modelling the interface controller for an inter-integrated controller channel (12C) bus in a mixed language (systemC and VHDL-AMS) and secondly, the real behaviour of this IP from a test bench on a hardware/software platform.