A behavioral fault simulator for Ideal
Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, R. Venkateswaran · IEEE Design & Test of Computers · 1992
A method of performing fault simulation at the behavioral level by propagating faults through behavioral hardware descriptions is presented. The method is accurate because it uses fault models only at the gate level. Since it does not duplicate computations at the behavioral level for each fault, it is, on the average, faster than existing methods. Examples in the Ideal hardware description language are used to discuss the basis for a fast behavioral fault simulator.>