A one-chip scalable 8*8 ATM switch LSI employing shared buffer architecture
Yasuro Shobatake, M. Motoyama, E. Shobatake, Takashi Kamitake, Susumu Shimizu, M. Noda, Kenji Sakaue · IEEE Journal on Selected Areas in Communications · 1991
The authors present a one-chip scalable 8*8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 mu m BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated.>