Reducing set-associative L1 data cache energy by early load data dependence detection (ELD 3 )
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors · 2014
Abstract—Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load operations for reduced access latency. This is required in order to resolve data depen-dencies as early as possible in the pipeline, which otherwise would suffer from stall cycles. A significant amount of energy is wasted due to this fast access, since the data can only reside in one of the ways. While it is possible to reduce L1 DC energy usage by accessing the tag and data memories sequentially, thereby activating only one data way on a tag match, this approach significantly increases execution time due to an increased number of stall cycles. We propose an early load data dependency detection (ELD3) technique for in-order pipelines that can detect if the load has a data dependency with a subsequent instruction that will cause stall cycles. If there is no such dependency, then the tag and data accesses for the load are sequentially performed so that only the data way in which the data resides is accessed. If there is a dependency, then the tag and data arrays are accessed in parallel to avoid introducing additional stall cycles. For the MiBench benchmark suite, the ELD3 technique enables about 49 % of all load operations to access the L1 DC sequentially. In a 65-nm physical implementation using commercial SRAM blocks, the proposed technique reduces L1 DC energy by 13%. I.