A reduced-space half-band filter design on an Actel FPGA
Linda S. DeBrunner, Victor DeBrunner, Xiaojuan Hu, Olivier Demuynck, A. Swartztrauber · 2001
This paper describes the application of our proposed method for low-space implementations of existing half-band FIR filter designs without loss of performance. We achieve greater than 16% reduction of space for a 22/sup nd/ order FIR filter. Further space saving is possible when more efficient multiplications are used. For a fixed-point VLSI implementation, finite wordlength behavior in digital filters is extremely important. Reducing the precision reduces the area consumed in the digital filter implementation at the cost of increasing the filter output quantization noise power. We propose a method suitable for use in VLSI and field programmable gate arrays (FPGAs) by scaling the real filter that reduces the precision of each coefficient. Our idea can be used in conjunction with any FIR digital filter design technique, and thus can be used to reduce the space required for any existing FIR filter.