A low-power 65-nm ASIC implementation of background subtraction
M. Sami Zitouni, Hani H. Saleh, Harish Bhaskar, Ehab Najeh Salahat, Mohammed A. Ismail · 2014
Background subtraction is an important step for object detection in many video processing systems. This paper presents a low power implementation of mean-filter based background subtraction block in ASIC flow using 65-nm CMOS process technology. The placed and routed ASIC implementation of the background subtraction block achieved an operating maximum frequency of 800MHz. This provides the system with the capability of processing HD video sequences, typically of spatial resolution 1920×1080 pixels at a potential rate of 385 fps. The background subtraction block occupied a total area of 1533.96μm2using 65-nm CMOS process and consumed a low power of 27.88μW/pixel.