A dynamic-time-warp integrated circuit for a 1000-word speech recognition system
R.A. Kavaler, Menahem Lowy, Hy Murveit, R.W. Brodersen · IEEE Journal of Solid-State Circuits · 1987
The design of a custom MOS-LSI chip capable of performing the pattern matching portion of a 1000-word speech recognition algorithm in real time is reported. The chip implements a dynamic-time-warp algorithm. The chip is part of a single-board speech recognition system that performs spectral analysis, dictionary storage and management, and speech recognition for both isolated and connected word applications of up to 1000 words. Speech recognition algorithms are normally refined to work well on general-purpose machines without the influence of future special-purpose hardware implementation. With general-purpose machines, chip implementation issues such as bit widths and parallelism cannot be utilized so they are ignored in favor of increasing algorithmic complexity by techniques such as pruning. If developed together, the chip architecture and algorithm can be refined to fully use parallelism and increasing throughput, while retaining efficient silicon area utilization. The resulting special-purpose architecture is sufficiently general that connected speech can be recognized without a speed penalty.