Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase
Cheng-Yuan Hsu, Chi-Wei Hung, Da Sung, Chi-Shan Wu, S.C. Chen, H.H. Kuo, Jun-You Pan, C.L. Chen, I.C. Chuang, Vincent Shi-Ming Huang, C.C. Hsue, D.-T. Fan, J.C. Lu, C.Y.-S. Cho, K. Tseng, A. Hsu, Bin-Nan Sheen, P. Tuntasood, Chiou-Feng Chen · 2004
For the first time, split-gate NAND flash memory featuring interpoly erase and mid-channel programming is demonstrated at 120nm technology node. The cell array operates at single polarity voltages lower than 12V. Erase and programming can be accomplished in 0.5ms and 10/spl mu/s, respectively.