Fault models of CMOS transmission gate
D. Milovanovic, Vanco B. Litovski · International Journal of Electronics · 1991
New CMOS transmission gate (TG) fault models are described. The TG is observed as a bilateral logic circuit. Its fault models are obtained using a mathematical circuit analysis of the elementary network and these are verified using the electronic circuit analysis rogram MOST. Another topic covered by the aper is faulty state ropagation through the TG. The results of the research described above enable successful fault simulation of circuits containing transmission gates