Estimating architectural resources and performance for high-level synthesis applications
Alok Sharma, Rajiv Ratan Jain · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993
The authors present a solution to the following problems related to architectural synthesis. (1) Given an input specification and a performance constraint, determine a lower bound number of resources (active and interconnect) required to execute the data flow graph while satisfying the performance constraint. (2) Determine a lower bound performance for executing an input specification for a given number of resources (active and interconnect). These bounds are close to the actual designs synthesized by several existing systems.>