Fault Diagnosis of MOS Combinational Networks
El-Ziq, Su · IEEE Transactions on Computers · 1982
The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.