A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method
Haoyuan Ying, Thomas Hollstein, Klaus Hofmann · 2014
Network-on-Chip (NoC) is proposed as the next generation interconnect technique for multi/many core embedded systems due to the high performance and scalability. An efficient and correct emulation method is significantly important for NoC system design and verification. In this paper, we would like to present a formalized and efficient hardware/software co-design method to emulate NoC system design configurations on FPGA. Our method is reconfigurable, flexible and platform-like. Resynthesizing the hardware NoC platform when only varying the target applications is unnecessary in our method. The hardware part of the emulation platform is generated automatically according to the input NoC specifications by our emulation supporting software. Different applications can be scheduled by the software and utilized for emulating the NoC hardware design. Besides the introduction of our emulation method, a demonstration of emulating NoC with different applications is also given.