Architecture for a high-speed standard basis GF(2m) multiplier with a constant primitive coefficient set
Sungsoo Choi, Youngkou Lee, Kiseon Kim · International Journal of Electronics · 2002
In this paper, a new high-speed semi-systolic GF(2m) multiplier based on the standard basis is designed and implemented. The basic multiplier cell in the semi-systolic multiplier is a type of generalized multiplier cell (GMC). It can be designed to have 2 one-bit pipelining latches and 5 symmetric input-and-output (I/O) ports, whereas the modified basic cell and LSB first multiplier developed by Jain and co-workers in 1995 and 1998 have 3 one-bit pipelining latches and 6 symmetric I/O ports. When a semi-systolic GF(28) multiplier with generalized multiplier cells (GMCs) is implemented, the hardware complexity is 26.9% lower than that of the multiplier with modified basic cells or the LSB first multiplier.