A 1.94mm2, 38.17mW dual VP8/H.264 Full-HD encoder/decoder LSI for Social Network Services (SNS) over smart-phones
Chi-Cheng Ju, Tsu-Ming Liu, Yi-Hau Chen, Kun-Bin Lee, Chia-Yun Cheng, Hsueh-Te Chao, Chih‐Ming Wang, Tung-Hsing Wu, Tin-An Lin, Han-Liang Chou, Yukun Lin, Cheng-Hung Liu, Wei-Cing Li, Yi-Hsin Huang, Tsung-Chuan Ma, Chun-Chia Chen, Hue-Min Lin, Min-Hao Chiu, Sheng-Jen Wang, Yung-Chang Chang · 2012
A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of web's video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm2of core area. Several area-efficient techniques are realized, leading to 43.6% of area reduction. A new rate control is designed to facilitate the adaptation of video data and frame rates for network services. Two fast algorithms and new bool encoder/decoder are proposed to enhance power efficiency. This chip consumes 28.15mW and 10.02mW of VP8 encoder and decoder average power for 1080p@30fps at 0.9V, respectively.