Mark IIIfp hypercube concurrent processor architecture
Jesus Ocampo Tuazon, John C. Peterson, Moshe Pniel · 1988
The Mark lllfp Hypercube is a new generation of hypercube concurrent processor system developed at JPL/Caltech, with peak performance of 5 Mips, 14 Mflops per node, and a peak communication rate of 6 Mbytes per second. Each node utilizes two Motorola MC68020 microprocessors, an MC68882 scalar floating- point coprocessor, and a Weitek 8000 floating-point chip set. One of the MC68020 processors serves as the application and computational processor, the other is dedicated to communication. The three processors are interconnected through a common system bus and share 4 Mbytes of dynamic memory. Each processor has his own fast local memory, which increases parallelism, minimizes shared memory referencing, reduces memory contentions and improves system performance.