Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)
André M. DeHon · 1999
4. Map circuits to a range of points in the interconnect space, and assess their total area and utilization.FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors.We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficient silicon usage.Rather, since interconnect resources consume most of the area on these devices (often SO-SO%), we can achieve more area efficient designs by allowing some LUTs to go unused-allowing us to use the dominant resource, interconnect, more efficiently.This extends the "Sea-ofgates" philosophy, familiar to mask programmable gate arrays, to FPGAs.Also introduced in this work is an algorithm for "depopulating" the gates in a hierarchical network to match the limited wiring resources. Examine relationship between LUT utilization and area. 2 Relation to Prior WorkMost traditional FPGA interconnect assessments have been limited to detailed population effects [1] [15].In particular, they let the absolute amount of interconnect (i.e.number of wiring channels or switches) float while assessing how closely a given population scheme allows detailed routing to approach the limit implied by global routing.They also assume that the target is to fully populate the LUTs in a region of the interconnect.