Learning hardware using multiple-valued logic - Part 1: introduction and approach
Marek A. Perkowski, D. Foote, Qihong Chen, Anas N. Al‐Rabadi, L. Jóźwiak · IEEE Micro · 2002
The authors propose a learning-hardware approach as a generalization of evolvable hardware. A massively parallel, reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation.