Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array
Joo Yun Seo, Yoon Kim, Se Hwan Park, Wandong Kim, Do-Bin Kim, Jong‐Ho Lee, Hyungcheol Shin, Byung‐Gook Park · 2012
In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).