A 0.4 ?m2 self-aligned AND-type flash memory cell technology
Tetsuo Adachi, Masataka Kato, Takashi Kobayashi, Yoshimi Sudo, Hitoshi Kume, Tadao Morimoto · Electronics and Communications in Japan (Part II Electronics) · 1997
Using self-alignment technology, a high-reliability, high-capacity, low power consumption AND-type flash memory was fabricated under the 0.25 μm design rule. In this new process, after the floating gate was formed, the diffused layers for device isolation, local bit line, and source line were formed by self-alignment. As a result, the mask alignment margin could be tighter and the cell area was reduced by 25% compared with that of a conventional device. The memory cell fabricated by this new process under the 0.25 μm design rule had an area of 0.4 μm2. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 2, 80(4): 85–91, 1997