Support vector machine coverage driven verification for communication cores
Edgar L. Romero, Raul Acosta, Marius Strum, Wang Jiang Chau · 2009
Making functional verification more efficient in terms of time and computing resources is necessary for the successful construction of future digital systems. Different functional coverage metrics have been proposed, as the modular (grey-box) coverage, in order to determine the end of testbench execution, with special importance for random stimulation based testbenches. Coverage driven verification (CDV) has shown to be successful reducing the time and the number of transactions required to achieve full functional coverage. The present study shows that, for the CDV tested in some communication systems under modular coverage, there is a loss of diversity in terms of testcase input parameter values. To overcome this problem, it is proposed the utilization of Support Vector Machine to perform CDV. Support vector machine is an artificial intelligence technique characterized by its high learning capability. The application of such a technique on CDV showed a testbench execution time compatible to other approaches such as Bayesian networks and data mining CDV, keeping the testcase's diversity higher.