Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models
Parthasarathy Ranganathan, Vijay S. Pai, Sarita V. Adve · 1997
This paper studies techniques to improue the performance of memory consistency models for shared-memory multiprocessors with ILP processors.The first part of this paper extends earlier work by studying the impact of current hardware optimization to memory consistency implementations, hardware-controlled non-binding prefetching and speculative load execution, on the performance of the processor consistency (PC) memory model.We find that the optimized implementation