The architecture of the HP Superdome shared-memory multiprocessor
Gary B. Gostin, Jean-François Collard⋆, Kirby Collins · 2005
This paper offers an overview of the HP Superdome shared memory multiprocessor, along with a detailed description of the cache coherence implementation. (An early and limited description was provided in [9].) We focus in particular on the sx1000 chipset, codenamed Pinnacles, which is used in HP's Integrity line of servers (Superdome Integrity, rx8620, rx7620) and in HP's 9000 series of PA-RISC based products (Superdome. rp8620, rp7420). The design goals for this architecture were to provide a platform that supported both PA-RISC and Itanium family processors, support multiple operating systems including HP-UX, Windows, and Linux, provide cache coherent scalability to large ways of MP. and support multiple product generations while preserving customer investments in memory and I/O infrastructure. This paper covers the system organization and network topology (Section 2), details on how processor instructions appear as coherence transactions (Section 3), the cache coherence protocol (Section 4). and microarchitectural details on the chipset (Section 5). It concludes with examples of application benchmarks that demonstrate the scalability achieved (Section 6).