Transaction level model of NoC based on SystemC
Wang Jian, Hong Wang, Zhi Jia Yang · 2009
This paper presents a transaction-level on-chip communication network model, including routers and links, which can be easily employed in a system-level system-on-chip simulation framework for early functional verification and architecture analysis. The model is capable of providing NoC's latency and throughput information during simulating process and developed in SystemC to achieve high simulation speed1.