Energy optimization of multi-level processor cache architectures
Uming Ko, Poras T. Balsara, Ashwini K. Nanda · 1995
To optimize performance and power of a processor's cache, a multiple-divided module (MDM) cache architecture is proposed to save power at memory peripherals as well as the bit array.For a MxB-divided MDM cache, latency is equivalent to that of the smallest module and power consumption is only 1/MxB of the regular, non-divided cache.Based on the architecture and given transistor budgets for onchip processor caches, this paper extends investigation to analyze energy effects from cache parameters in a multi-level cache design.The analysis is based on execution of SPECint92 benchmark programs with miss ratios of a RISC processor.