Hardware/software tradeoffs in a variable word width, variable queue length buffer memory
Alice C. Parker, Andrew W. Nagle · ACM SIGARCH Computer Architecture News · 1977
This paper describes a buffer memory design which is integratable on a single 40 pin package. The memory consists of four variable word width, variable length queues, address logic, and logic for configuring the data widths and queue lengths. Simple program commands input on the data lines reconfigure the memories when the circuit is in program mode. In data mode, WRITE and READ requests to a particular buffer enable the memory to load and access itself, update its pointers, and check for full, empty, and bottom of queue conditions. This design is compared to software methods for queue maintenance. Speed of operation, in terms of memory cycles and register transfers is compared for the two methods, and the hardware complexity of both methods is discussed. A short discussion of hard and software tradeoffs is followed by conclusions.