750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC Min-Sum based analog decoder
Alireza Rabbani Abolfazli, Yousef R. Shayan, Glenn E. R. Cowan · 2013
Circuit and IC implementation of a (120, 75) Min-Sum based Turbo-Structured LDPC analog decoder in CMOS 90nm technology is presented. This is the highest throughput and one of the longest codes implemented to date using analog techniques. At a Bit Error Rate of 10-5, the measured performance is within 0.2dB of modeled performance using floating-point arithmetic. The chip was tested at a throughput of 750Mb/s. This improves the throughput of analog decoders by a factor of 57. The power dissipation of the core is 13 mW resulting in 17pJ/b energy efficiency. The core area is 1.38mm2. The fabricated MS-based TS-LDPC analog decoder has BER performance nearly identical to theory without compromising energy efficiency.